1. Field of the Invention
The present invention refers to methods of adjusting a phase shift between a data signal and a clock signal, and to devices providing an adjustment of a phase shift between a data signal and a clock signal.
2. Description of the Related Art
In graphics applications and in other applications the data rate of the exchange of data between a memory controller and a memory device is increased more and more. According to the GDDR5-standard, the data rate will be up to 4 Gbit/s/pin or even 5 Gbit/s/pin. With data rates like these, the timing of the signals relative to the clock is a serious challenge. Any unforeseen delay of a data signal or of a clock signal drastically increases the error rate in the data detection at the receiver.
An automatic adjustment mechanism could reduce the static mismatches between the propagation paths of each single data signal and a clock signal. Thereby, voltage and temperature dependent drifts could be compensated to a certain level. However, neither present nor already projected future DRAM standards provide any mechanism for returning information about the phase alignment at the receiving memory device to the memory controller.
One way to obtain information about the phase alignment at the receiving memory device consists in writing specific data patterns repeatedly to the memory device with different values of a phase shift between the sent data signal and the clock signal. For each value of the phase shift, the data pattern is then read from the memory device, transferred into the memory controller and compared with the originally sent data pattern. A data phase window with error free transmission is identified and an optimum write phase is chosen within this window.
However, the circuitry for this solution is quite complex, in particular the computations are time consuming and require special circuitry in the memory controller. Thereby the costs of production of the memory controller are increased. Furthermore, the described solution utilizes memory space of the memory device. Application data stored in this memory space needs to be swapped to another memory space and restored afterwards.